Anusha |
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Anil |
BE in Electronics and Communication and M.Tech in VLSI Design and Embedded Systems. |
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Work-18 months. |
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Verification-18 months. |
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Verilog---------------18 months |
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System Verilog,UVM-04 months. |
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Tools working/worked -ModelSim, QuestaSim, Cadence NCSim, Cadence Incisive Simulator. |
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Company worked with- STMicroelectronics for 12 months. |
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BE in Electronics and Communication and M.Tech in VLSI & Embedded systems |
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Work -16 months |
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VLSI designing-12 months |
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Verilog coding-12 months |
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Tools worked cadence virtuoso-12 months |
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Spectre simulator-12 months |
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Pspice simulator-12 months |
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Physical Verification tool - mentor graphic calibre -12 months. |
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Company worked with-12 months in INTEL |
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Bakkesh |
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Mahantesh |
BE in Electronics and Communication MTech in VLSI Design and Embedded Systems. |
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Work-6 months |
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VLSI designing-06 months |
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VLSI Devloping-06 months. |
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Tools-Xilinx ISE 13.1 edition. |
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Simulation tools-ISim software and ModelSim software. |
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BE in Electronics and Communication. |
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Work-41 months. |
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Design and Development-41 months. |
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8/16/32 bit ARM Controller-41 months. |
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C and Assembly Coding -41 months using KIEL, & Code warrior. |
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Tools Worked-41 months using KIEL, Code warrior, & Code editor. |
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Tools working-KIEL, Code warrior, & Code editor. |
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Companies worked with-Savinirs InfoTech pvt.LTD. |
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Manjunath |
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Sagar |
BE in Electronics and Communication and MTech in VLSI Design and Embedded Systems. |
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Work-6 months. |
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VLSI Designing-6 months using verilog. |
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Tools Worked-6 months on Synopsis(VCS,DC,PT). |
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Tools working-Xilinx13.1. |
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BE in Electronics and Communication and MTech in VLSI Design and Embedded Systems. |
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Work- 6 months. |
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Analysing Design-12 months. |
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Tools Worked-6 months on Synopsis(VCS,DC,PT). |
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VLSI Designing-06 months using verilog. |
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Tools working-Xilinx13.1. |
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Sharath Kumar |
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Vinod |
BE in Electronics and Communication and MTech in VLSI Design and Embedded Systems. |
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Work-26 months. |
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Scripting-03 months. |
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Designing-12 months. |
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Verification-12 months. |
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Verilog-24 months. |
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Sys verilog-18 months. |
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VHDL-12 months. |
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Pearl-03 months. |
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Tools working/worked with-Modelsim, questasim, ncsim, vcs. |
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Companies worked with-Renesas mobile, arasan chips. |
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Electronics and Communication and MTech in VLSI Design and Embedded systems. |
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Work-12months. |
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Scripting-Perl ,TCL. |
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Verification-12 months Block level verification in Intel. |
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Language used-Verilog, System Verilog and VHDL. |
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Tool Used-NCSIM and QUESTASIM for Verification. |
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Tool using Now-NCSIM. TESTKOMPRESS(ATPG),ET-LV for MBIST ,RC and DC for scan insertion. |
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Pramod |
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BE in Electronics and Communication and MTech in VLSI Design and Embedded systems |
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Work-18 months. |
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Scripting-TCL. |
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VLSI Designing-12 months in Bright Electronics. |
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Languages-18 months Verilog, VHDL, MatLab programming. |
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Tools Worked with-06 months VCS, DC, PT, DFT, ICC(Synopsis), MatLab/Simulink. |
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-02 months NS2. |
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-12 months Cadence virtuoso. |
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Tools Working-Xilinx 13.1,Modelsim ISE simulator, Cadence virtuoso |
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